The Computing Earthquake: Neural Networks, Cognitive Layering and Energy-Driven Compute in Electronic Systems

Date: Chris RowenTuesday, November 17th, 2015, 6:30 PM
Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (map)
Speaker: Dr. Chris Rowen, Chief Technology Officer, IP Group, Cadence

Time: 6:30 PM (PT) Networking/Refreshments, 7:00 PM Presentation


A set of profound changes are clearly underway in computing. New computational models like convolutional neural networks for pattern recognition are replacing programming with training. Responsive systems are evolving new hardware and software layers that shift the most commonly executed functions to low-power subsystems – even while driving richer functionality into less-frequently functions into the cloud.

Distributed applications are not just spread across multiple processors on a chip, or multiple boards in a rack, but distributed across mobile and IoT devices, network gateways and servers sometimes on the opposite side of the globe from the user. These radically distributed systems drive a dramatic readjustment of trade-offs between computing and communication. Taken together, these changes represent a seismic shift in the computing landscape, with a new imperative to closely understand the flow of data, the energy cost of computing and alternatives to conventional software development.

Slides  from the Talk

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Speaker Bio

Dr. Chris Rowen is the Chief Technology Officer for Cadence’s IP Group. He is developing extensible processor IP that can be configured easily into custom chips for applications in wireless, peripheral control, imaging, and other areas. He joined Cadence after its acquisition of Tensilica, the company he founded to develop extensible processors. He built Tensilica to the point where its processors had more than 200 licensees, including seven of the top 10 chip companies, who had shipped more than 2 billion cores. Before founding Tensilica, he was VP and General Manager of the Design Reuse Group at Synopsys. He also was a pioneer in developing RISC architecture and helped start MIPS Computer Systems, where he was Vice President for Microprocessor Development. He holds an MSEE and PhD in electrical engineering from Stanford (working under John Hennessy) and a BA in physics from Harvard.

Note : The doors close at 7:30 PM

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