Monthly Archives: October 2017

Bay Area Multimedia Meetup Group: A Technical Overview of AV1 Video Codec from Open Media Alliance

Bay Area Multimedia Meetup Group presents:

A Technical Overview of AV1 Video Codec from Open Media Alliance

Date: Thursday, November 9th, 2017

Speaker: Debargha Mukherjee, Ph.D and Jingning Han, Ph.D

Time: 6:00 PM (PT)

Location: Cisco Building J
255 West Tasman Drive, San Jose, CA (map)


Google embarked on the WebM Project in 2010 to develop open source, royalty-­free video codecs designed specifically for media on the Web. The second generation codec released by the WebM project, VP9, ­is currently served by YouTube, and enjoys billions of views per day. Realizing the need for even greater compression efficiency and to cope with the ever-increasing demand for video on the web, the WebM team started an ambitious project to develop a next edition royalty-free codec AV1, in a consortium of major tech companies called the Alliance for Open Media. The goal of AV1 is to achieve a generational improvement in coding efficiency over VP9 at a practical hardware and software complexity, and is scheduled to be finalized by the end of 2017. In this talk, we will provide a technical overview of the major prediction, transform and in-loop filtering tools under consideration in AV1. Preliminary results will be presented on standard test sets.

Speaker Bio

Debargha Mukherjee
Debargha Mukherjee received his M.S./Ph.D. degrees in ECE from University of California Santa Barbara in 1999. Thereafter, through 2009 he was with Hewlett Packard Laboratories, conducting research on video/image coding and processing. Since 2010 he has been with Google Inc., where he is currently involved with open-source video codec development. Prior to that he was responsible for video quality control and 2D-3D conversion on YouTube. Debargha has authored/co-authored more than 80 papers on various signal processing topics, and holds more than 40 US patents, with several more pending. He has delivered many workshops and talks on Google’s VPx line of codecs since 2012. He currently serves as an Associate Editor of the IEEE Trans. on Circuits and Systems for Video Technology and has previously served as Associate Editor of the IEEE Trans. on Image Processing; he is also a member of the IEEE Image, Video, and Multidimensional Signal Processing Technical Committee (IVMSP TC).

Jingning Han
Jingning Han received the B.S. degree in Electrical Engineering from Tsinghua University in 2007, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from University of California Santa Barbara in 2008 and 2012, respectively. He is with the WebM codec team at Google and is an architect for the VP9 and AV1 codec. His research interests include video coding and computer architecture. Dr. Han was a recipient of the Best Student Paper Award at the IEEE International Conference on Multimedia and Expo in 2012. He received the IEEE Signal Processing Society Best Young Author Paper award in 2015.

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Energy-Efficient RISC-V Processors in 28nm FDSOI

Energy-Efficient RISC-V Processors in 28nm FDSOI

Borivoje Nikolic

Date: Tuesday, November 14th, 2017

Speaker: Prof. Borivoje Nikolic
University of California, Berkeley

Time: 6:30 PM (PT) Networking/Refreshments,
7:00 PM Presentation.

Location: Cadence / Bldg 10,
2655 Seely Ave, San Jose, CA (map)


This talk presents the design of a series of energy-efficient microprocessors done by a group of students at UC Berkeley. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the designs feature an integrated switched-capacitor DC-DC converter and direct power measurement, with an integrated power-management unit. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Speaker Bio

Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley. He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis in 1999. His research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003. Dr. Nikolić received many awards in his career, including the NSF CAREER award in 2003, and the best paper awards at the IEEE International Solid- State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Circuits Research Conference, European Solid-State Device Research Conference, S3S conference and the ACM/IEEE International Symposium of Low- Power Electronics.


Eventbrite - Energy-Efficient RISC-V Processors in 28nm FDSOI

Note : The doors close at 7:30 PM

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