Monthly Archives: March 2018

Developing Fully Automated Infrastructure Policy and Trust Systems

April 3, 2018, 6:00-8:00PM

Speakers:

  • Mike Dvorkin

Distinguished Engineer at Cisco

  • Andres Vega

Engineering Product Manager at Cisco

Location: Cadence / Bldg 10,
2655 Seely Ave, San Jose, CA (map)

(Register here)

IEEE Computer Society of Silicon Valley

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:

Modern infrastructure management serves to run applications, but in many cases, all attention is spent on micromanagement of elemental details with no focus or understanding of the applications. This breaks down in two fundamental ways. First is the explosion of number of application service definitions, all hardwired for specific use cases, environments, and circumstances related to the stage of the application life cycle. Second is the dependency chaos resulting from lack of mechanisms to control consumption of application services. These problems are closely related. The missing piece is how service resources are allocated to their consumers and how such allocations can be controlled in a consistent, secure, abstracted way devoid of understanding of instance, architecture, and environmental detail. By introduction of automated policy and trust systems, the administrative overhead of managing infrastructure is reduced by putting operations on autopilot consistent with and governed by specified service-specific policies and consumption rules.

Bios:

    • Mike Dvorkin

Mike Dvorkin is Distinguished Engineer at Cisco. Previously co-founder and Chief Scientist at Insieme Networks and lead Systems Architect at Nuova Systems. Mike is a recognized thought leader in distributed systems, and policy-driven automation and operations.

    • Andres Vega

Andres Vega is Engineering Product Manager at Cisco primarily focused on the intersection of Cloud and Data Center Infrastructure with open source projects such as the Linux kernel, Linux containers, and container orchestration frameworks like Kubernetes, seeking to drive innovation in open, secure, and programmable infrastructure to contribute to the solution of complex distributed system problems.

Open to all to attend

(Online registration is needed. If you did not register, seating is not guaranteed.)

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Fabric for Deep Learning (FfDL)

April 24, 2018, 6:00-8:00PM

Animesh Singh
STSM – AI and Deep Learning on Cloud
Member of IBM Academy of Technology, San Jose

Location:
ITU Auditorium, International Technological University
2711 N 1st St., San Jose, CA 95134

 (Register here)

IEEE Computer Society of Silicon Valley 

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:

Training deep neural network models requires a highly tuned system with the right combination of software, drivers, compute, memory, network, and storage resources.

Deep learning frameworks such as TensorFlow, PyTorch, Caffe, Torch, Theano, and MXNet have contributed to the popularity of deep learning by reducing the effort and skills needed to design, train, and use deep learning models. Fabric for Deep Learning (FfDL, pronounced “fiddle”) provides a consistent way to run these deep-learning frameworks as a service on Kubernetes.

In this talk we are going to introduce an open source project called Fabric for Deep Learning (FfDL). It uses a microservices architecture to reduce coupling between components, keep each component simple and as stateless as possible, isolate component failures, and allow each component to be developed, tested, deployed, scaled, and upgraded independently.

Bio:

Animesh Singh is an STSM and Program Director for IBM Watson and Cloud Platform, currently leading Machine Learning and Deep Learning initiatives on IBM Cloud. He has been with IBM for more than a decade and is currently working with communities and customers to design and implement Deep
Learning, Machine Learning and Cloud Computing frameworks. He has been leading cutting edge projects for IBM enterprise customers in Telco, Banking, and Healthcare Industries, around cloud and virtualization technologies. He has a proven track record of driving design and implementation of private and public cloud solutions from concept to production. He also led the design and development first IBM public cloud offering, and was the lead architect for Bluemix Local. Find Animesh on Twitter @AnimeshSingh.

Animesh Singh

Animesh Singh

Venue:

ITU Auditorium, International Technological University
2711 N 1st St., San Jose, CA 95134

  • Theater style auditorium, capacity 250 people
  • Free parking at the ITU, first-come, first-serve basis
  • Attendees can only enter the building via the main entrance.
  • All attendees are required to check in at the front desk.
  • Food and drinks will be provided

Open to all to attend
(Online registration is needed. If you did not register, seating is not guaranteed.)

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50 Years of Computer Architecture: From Mainframe CPUs to DNN TPUs and Open RISC-V

Thursday March 15, 2018, 6:00-8:00PM

Prof. David Patterson, Google & University of California, Berkeley

Location:
Texas Instruments Silicon Valley Auditorium
2900 Semiconductor Dr., Building E, Santa Clara, CA (Register here)

IEEE Santa Clara Valley Section

PROGRAM

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:

This talk reviews a half-century of computer architecture: We start with the IBM System 360, which in 1964 introduced the concept of “binary compatibility”. Next, came the idea of the “dominant microprocessor architecture”, for which the early candidate was the Intel 432 which was shortly replaced by the emergency introduction of the Intel 80×86 in 1978. However, for the next 20 years, the Reduced Instruction Set Computers (RISC) became dominant. Then, the Very-Long-Instruction-Word (VLIW) HP/Intel Itanium architecture was heralded as their replacement in 2001, but instead the role was usurped by AMD’s introduction of the 64-bit 80×86. Thus, while the 80×86 dominated the PC-Era, RISCs have led thereafter, currently with 20B shipped annually (versus 0.4B 80x86s). Since the ending of Moore’s Law and Dennard scaling has stalled performance of general-purpose microprocessors, domain-specific computer architectures are the only option left. An early example of this trend introduced by Google in 2015 is the Tensor Processing Unit (TPU) for cloud-based deep neural networking. The widespread agreement about instruction sets has led to the open architecture RISC-V (“RISC Five”), which has been embraced by more than 100 members of the RISC-V Foundation. RISC-V and accelerators like the TPU demark a new renaissance for computer architecture.

Bio:

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976. He is also a Distinguished Engineer at Google, where he helps with accelerators for machine learning.
Dave’s research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of faculty and graduate students to answer them. The answer is typically embodied in demonstration systems, and these demonstration systems are later mirrored in commercial products. In addition to research impact, these projects train leaders of our field. The best-known projects were Reduced Instruction Set Computers (RISC), Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW), each of which helped lead to billion dollar industries.
A measure of the success of projects is the list of awards won by Patterson and as his teammates: the C & C Prize, the IEEE von Neumann Medal, the IEEE Johnson Storage Award, the SIGMOD Test of Time award, the ACM-IEEE Eckert-Mauchly Award, and the Katayanagi Prize. He was also elected to both AAAS societies, the National Academy of Engineering, the National Academy of Sciences, the Silicon Valley Engineering Hall of Fame, and to be a Fellow of the Computer History Museum. The full list includes about 35 awards for research, teaching, and service.
In his spare time, he coauthored seven books, including two architecture texts with John Hennessy, who is past President of Stanford University. Patterson also served as Chair of the Computer Science Division at UC Berkeley, Chair of the Computing Research Association, and President of ACM.

Venue:

Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Building E, Santa Clara, CA 95051 Directionsand Map (to locate Building E).

Admission Fee:

Open to all to attend
(Online registration is needed. If you did not register, seating is not guaranteed.)

IEEE SSCS/CAS/CS/SPS/CIS society members – FREE
Students – $3 (Register at Door $3)
IEEE (non-society) members – $7 (Register at Door $10)
Non-members – $10 (Register at Door $15)
You do not need to be an IEEE member to attend!

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