“Plasticine: A Reconfigurable Dataflow Architecture for Software 2.0”

Thursday, April 18, 2019, 6:00 PM – 8:00 PM PDT
 
Speaker: Prof. Kunle Olukotun, Stanford University/SambaNova Systems
   
. Computer Society(CS)     
. Solid-State Circuits Society(SSCS)    
. Signal Processing Society(SPS) 
. Computational Intelligence Society (CIS/Artificial Intelligence)
 
Location:

Texas Instruments Silicon Valley Auditorium
2900 Semiconductor Dr.
Building “E”
Santa Clara, CA 95051
View Map
 
(Register here)
 
PROGRAM
6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Abstract:
The use of machine learning to generate models from data is replacing traditional software development for many applications. This fundamental shift in how we develop software, known as Software 2.0, has provided dramatic improvements in the quality and ease of deployment for these applications. The continued success and expansion of the Software 2.0 approach must be powered by the availability of powerful, efficient and flexible chips that are tailored for machine learning applications. This talk will describe a design approach that optimizes computer systems to match the requirements of machine learning applications. The full-stack design approach integrates machine learning algorithms that are optimized for the characteristics of applications and the strengths of modern hardware, domain-specific languages and advanced compilation technology designed for programmability and performance, and a reconfigurable dataflow architecture called Plasticine that achieve both high flexibility and high energy efficiency.

Plasticine is a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns. I will describe the Plasticine architecture: the compute pipeline that exploits nested parallelism, the configurable memory system that captures data locality and sustains compute throughput with multiple banking modes, and the on-chip interconnect that supports communication at multiple levels of granularity.
 
Bio:
Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is well known as a pioneer in multicore processor design and the leader of the Stanford Hydra chip multipocessor (CMP) research project. Olukotun founded Afara Websystems to develop high-throughput, low-power multicore processors for server systems. The Afara multicore processor, called Niagara, was acquired by Sun Microsystems. Niagara derived processors now power all Oracle SPARC-based servers. Olukotun currently directs the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate the use of heterogeneous parallelism in all application areas using Domain Specific Languages (DSLs). Olukotun is a member of the Data Analytics for What’s Next (DAWN) Lab which is developing infrastructure for usable machine learning. Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design and is the recipient of the 2018 IEEE Harry H. Goode Memorial Award. Olukotun received his Ph.D. in Computer Engineering from The University of Michigan.
 
Admission Fee:
Open to all to attend(Online registration is needed. If you did not register, seating is not guaranteed.)
Non-members – $5 (Register at Door $15)
IEEE SSCS/CAS/CS/SPS/CIS society members – FREE
Students – FREE
IEEE (non-society) members – FREE (Register at Door $10)
You do not need to be an IEEE member to attend!

Update: Presentation slides/videos of this event are now available at http://sites.ieee.org/scv-sscs/previous-events/april-18-2019/ 

 

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